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this is information on a product in full production. october 2013 docid024229 rev 3 1/58 stts2004 2.2 v memory module temperature sensor with a 4 kb spd eeprom datasheet - production data features ? 2.2 v memory module temperature sensor with integrated 4 kb spd eeprom ? fully compliant with jedec tse2004b2 specifications ? operating temperature range: ?20 c to +125 c ? single supply voltage 2.2 v to 3.6 v ? 2 mm x 3 mm tdfn8, height: 0.80 mm (max): jedec mo-229, w2030d compliant rohs compliant, halogen-free temperature sensor ? temperature sensor resolution: programmable (9-12 bits) 0.25 c (typ)/lsb - (10-bit) default ? temperature sensor accuracy (max) of: 1 c (from +75 c to +95 c); 2 c (from +40 c to +125 c); 3 c (from ?20 c to +125 c) ? adc conversion time: 125 ms (max) / 70 ms (typ) at default resolution (10-bit) ? typical operating supply current 160 a (eeprom standby) ? temperature hysteresis selectable set points from 0, 1.5, 3, 6.0 c 4 kb spd eeprom ? functionality identical to st?s m34e04 spd eeprom ? 4 kbits organized as two pages of 256 bytes each ? each page is composed of two 128-byte blocks ? software data protection for each 128-byte block ? byte write within 5 ms ? 16 bytes page write within 5 ms ? more than 1 million write cycles ? more than 40-year data retention two-wire bus ? two-wire i 2 c compatible serial interface ? supports up to 1 mhz transfer rate (i 2 c fast mode+) ? does not initiate clock stretching ? supports smbus timeout 25 ms - 35 ms tdfn8 2 mm x 3 mm (max height 0.80 mm) www.st.com
contents stts2004 2/58 docid024229 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 device type identifier (dti) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 i 2 c slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 a0, a1, a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 sda (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.5 event (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.6 v dd (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 i 2 c communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 smbus/i 2 c ac timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.3 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.5 event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 temperature trip point registers (read/write) . . . . . . . . . . . . . . . . . . . . . . 27 4.4.1 alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.2 critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.5 manufacturer id register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 device id and device revision id register (read-only) . . . . . . . . . . . . . . . 30 4.7 temperature resolution register (read/write) . . . . . . . . . . . . . . . . . . . . . . 30
docid024229 rev 3 3/58 stts2004 contents 58 4.8 smbus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 4 kb spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 internal device reset - spd eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.1 set and clear the write protection (swpn and cwp) . . . . . . . . . . . . . . 34 5.4.2 rpsn: read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.3 span: set spd page address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.4 rpa: read spd page address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5.3 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . 36 5.6 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 programming the spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.1 isolated dimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.2 dimm inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 41 7 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
list of tables stts2004 4/58 docid024229 rev 3 list of tables table 1. logical serial address according to a2, a1, a0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. legend for figure 9: event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. temperature register coding examples (for 10 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 16. temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 20. manufacturer id register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 21. device id and device revision id register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. temperature resolution register (tres) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. tres details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 25. dram dimm connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 26. acknowledge when writing data or defining the write-protection status (instructions with . . . r/w_n bit = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 27. acknowledge when reading the protection status (instructions with r/w_n bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 28. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 29. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 30. dc characteristics - temperature sensor component with eeprom . . . . . . . . . . . . . . . . . 44 table 31. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 32. temperature to digital conversion performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 33. ac characteristics of stts2004 for smbus and i 2 c compatibility timings. . . . . . . . . . . . . 47 table 34. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) . . . . . . . . . . 50 table 35. parameters for landing pattern - tdfn8 package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 36. carrier tape dimensions tdfn8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 37. reel dimensions for 8 mm carrier tape - tdfn8 package . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 38. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 39. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
docid024229 rev 3 5/58 stts2004 list of figures 58 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. tdfn8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. i2c write to pointer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. i 2 c write to pointer register, followed by a read data word . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. i 2 c write to pointer register, followed by a write data word. . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 10. smbus timeout timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 11. stts2004 reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 18. smbus/i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19. maximum r pu value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 20. pull-up resistor values versus bus line capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 21. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) . . . . . . . . . . 50 figure 22. dn package topside marking information (tdfn8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 23. landing pattern - tdfn8 package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24. carrier tape for tdfn8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 25. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
description stts2004 6/58 docid024229 rev 3 1 description the stts2004 is targeted for ddr4 dimm modules in servers, desktops, and mobile personal computing platforms (laptops and other industrial applications). the thermal sensor (ts) in the stts2004 is compliant with the jedec specification tse2004a2, which defines memory module thermal sensor requirements for use in dram dimms (dual inline memory modules) with serial presence detect (spd), in which all the information concerning the dram module configuration (such as access speed, size, and organization) can be kept write-protected in one or more of the blocks of memory. the 4-kbit serial eeprom (spd) in the stts2004 is organized as two pages of 256 bytes each, or 512 bytes of total memory. each page is comprised of two 128-byte blocks. the spd is able to selectively lock the data in any or all of the four 128-byte blocks. the stts2004 can interface to buses which have multiple devices on a shared bus, and each device has its own unique address on this bus. the device can achieve substantial power savings by using the software-programmed shutdown mode. the ts-spd eeprom combination provides space as well as cost savings for mobile and server platform dual inline memory modules (dimm) manufacturers, as it is packaged in the compact 2 mm x 3 mm 8-lead tdfn package with a thinner maximum height of 0.80 mm. the dn package is compliant to jedec mo-229, variation w2030d. the digital temperature sensor has a programmable 9-12 bit analog-to-digital converter (adc) which monitors and digitizes the temperature to a resolution of up to 0.0625 c. the default resolution is 0.25 c/lsb (10-bit). the typical accuracies over these temperature ranges are: 2 c over the full temperature measurement range of ?20 c to 125 c 1 c in the +40 c to +125 c active temperature range, and 0.5 c in the +75 c to +95 c monitor temperature range the temperature sensor in the stts2004 is specified for operating at supply voltages from 2.2 v to 3.6 v. operating at 3.3 v, the typical supply current is 160 a (includes i 2 c communication current). the on-board sigma-delta adc converts the measured temperature to a digital value that is calibrated in c. for fahrenheit applications, a lookup table or conversion routine is required. the stts2004 is factory-calibrated and requires no external components to measure temperature. the digital temperature sensor component has user-programmable registers that provide the capabilities for dimm temperature-sensing applications. the open drain event output pin is active when the monitoring temperature exceeds a programmable limit, or it falls above or below an alarm window. the user has the option to set the event output as a critical temperature output. this pin can be configured to operate in either a comparator mode for thermostat operation or in interrupt mode. the stts2004 is protocol-compatible with the 2 kbit spd in the stts2002 and uses a page selection method which is applied to the lower or upper pages of the 4 kbit spd. unlike the stts2002, the stts2004 does not support the permanently set write protect (pswp) feature. locking a 128-byte block of the eeprom is accomplished by using a software write protection mechanism in conjunction with a high input voltage v hv on the a0 input pin. a specific i 2 c sequence is used to protect each block from writes until write protection is
docid024229 rev 3 7/58 stts2004 description 58 electrically reversed using a separate i 2 c sequence which also requires v hv on input a0 pin of the device. write protection for all four blocks is cleared simultaneously, and write protection may be re- asserted after being cleared.
serial communications stts2004 8/58 docid024229 rev 3 2 serial communications the stts2004 has a simple 2-wire i 2 c-compatible digital serial interface which allows the user to access both the 4 kb serial eeprom and the data in the temperature register at any time. it communicates via the serial interface with a master controller which operates at speeds of up to 1 mhz. it also gives the user easy access to all of the stts2004 registers in order to customize device operation. the device behaves as a slave device in the i 2 c protocol, with all operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and r/w bit (as described in table 2 on page 10 ), terminated by an acknowledge bit. the stts2004 device is selected when decoding the correct device select byte. the device select byte is comprised of the 4-bit device type identifier (dti) and the 3-bit select address. the spd and ts portions of the stts2004 device are designed to operate in parallel. accesses to each portion of the device may be interleaved as long as the command protocol is followed. when writing data to the memory, the stts2004 inserts an acknowledge bit during the 9 th clock cycle, following the bus master's 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a bus master generated stop condition after an ack for write, and after a no ack for read. the ts portion of the stts2004 device uses a pointer register to access all registers in the device. additionally, all data transfers to and from this section of the device are performed as block read/write operations. the data is transmitted/received as 2 bytes, most significant byte (msb) first, and terminated with a no ack and stop after the least significant byte (lsb). data and address information is transmitted and received most significant bit first. note: clock stretching is not supported by the device. violations of the command protocol result in unpredictable operation. 2.1 device type identifier (dti) code the jedec temperature sensor and eeprom each have their own unique i 2 c address, which ensures that there are no compatibility or data translation issues. this is due to the fact that each of the devices have their own 4-bit dti code, while the remaining three bits are configurable. this enables the eeprom and thermal sensors to provide their own individual data via their unique addresses and still not interfere with each other?s operation in any way. the ts registers of the stts2004 are accessed using a dti of (0011). a0, a1, and a2 inputs are directly combined with the dti and the spd page address bit to qualify i 2 c addresses. each of the address pins (a0, a1, a2) is tied to v dd or v ss for the logical serial address (lsa) which is equal to the code on the address pins (refer to table 1 ).
docid024229 rev 3 9/58 stts2004 serial communications 58 the spd memory may be accessed using a dti of (1010), and to perform the swpn, rspn, or cwp operations, a dti of (0110) is required. the dti codes are: ? '0011' for the ts, and ? '1010' for addressing the eeprom memory array, and ? ?0110? to access the software write protection settings of the eeprom 2.1.1 i 2 c slave sub-address decoding the 7-bit address for stts2004 device consists of the 4-bit dti code and the 3-bit device select code from the state of the 3 address pins (device select code) which are combined as shown in table 2 . the 8 th bit is the read/write bit (r/w). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. the physical address for the ts is different than that used by the eeprom. the ts physical address is binary 0 0 1 1 a2 a1 a0 rw, where a2, a1, and a0 are the three slave sub- address pins, and the lsb "rw" is the read/write flag. the eeprom physical address is binary 1 0 1 0 a2 a1 a0 rw for the memory array and is 0 1 1 0 a2 a1 a0 rw for permanently set write protection mode. thus up to eight stts2004 devices can be connected on a single i 2 c bus. each device is given a unique 3-bit logical serial address code. the lsa is a decoding of information on the address pins a0, a1, and a2 as described in table 1 . when the device select code is received, the device only responds if the select address is the same as the logical serial address. table 1. logical serial address according to a2, a1, a0 write protection commands swpn, cwp, and rpsn, and the spd page address commands span and rpa, do not use the select address a(n) or logical serial address (lsa), therefore all devices on the bus will act on these commands simultaneously. since it is impossible to determine which device is responding to rpsn or rpa commands, for example, these functions are primarily used for external device programmers rather than in- system applications. logical serial address (lsa) device select code a2 a1 a0 000 0 (v ss ) 0 (v ss ) 0 (v ss ) 001 0 (v ss ) 0 (v ss ) 1 (v dd ) 010 0 (v ss ) 1 (v dd ) 0 (v ss ) 011 0 (v ss ) 1 (v dd ) 1 (v dd ) 100 1 (v dd ) 0 (v ss ) 0 (v ss ) 101 1 (v dd ) 0 (v ss ) 1 (v dd ) 110 1 (v dd ) 1 (v dd ) 0 (v ss ) 111 1 (v dd ) 1 (v dd ) 1 (v dd )
serial communications stts2004 10/58 docid024229 rev 3 table 2. device select code function symbol device type identifier (dti) (1) logical serial address (lsa) (2)(3) r/w a0 pin (4) b7 b6 b5 b4 b3 b2 b1 b0 read temperature registers rtr 0 0 1 1 a2 a1 a0 1 0 or 1 write temperature registers wtr 0 read ee memory rspd 1 0 1 0 a2 a1 a0 1 0 or 1 write ee memory wspd 0 set write protection, block 0 swp0 01 1 0 0010 v hv set write protection, block 1 swp1 1 0 0 0 v hv set write protection, block 2 swp2 1 0 1 0 v hv set write protection, block 3 swp3 0 0 0 0 v hv clear all write protection cwp 0 1 1 0 v hv read protection status, block 0 (5) rps0 0 0 1 1 0, 1 or v hv read protection status, block 1 (5) rps1 1 0 0 1 0, 1 or v hv read protection status, block 2 (5) rps2 1 0 1 1 0, 1 or v hv read protection status, block 3 (5) rps3 0 0 0 1 0, 1 or v hv set ee page address to 0 (6) spa0 1 1 0 0 0, 1 or v hv set ee page address to 1 (6) spa1 1 1 1 0 0, 1 or v hv read ee page address (7) rpa 1 1 0 1 0, 1 or v hv reserved -- all other encodings 1. the most significant bit, b7, is sent first. 2. logical serial addresses (lsa) are generated by the combination of inputs on the address pin (refer to table 1 ) 3. for backward compatibility with previous devices, the order of block select bits (b3 and b1) are not a simple binary encoding of the block number 4. a0 pin is driven to 0 = v ss , 1 = v dd or v hv . 5. reading the block protection status results in ack when the block is not write-protected, and results in noack when the block is write-protected. 6. setting the spd (eeprom) page address to 0 selects the lower 256 bytes of eeprom, setting to 1 selects the upper 256 bytes of eeprom. subsequent read ee or write ee commands operate on the selected ee page. 7. reading the ee page address results in ack when the current page is 0 and nack when the current page is 1.
docid024229 rev 3 11/58 stts2004 serial communications 58 figure 1. logic diagram 1. sda and event are open drain. note: the stts2004 also has a heat paddle, which is typically connected to the application ground plane, refer to figure 23: landing pattern - tdfn8 package (dn) . figure 2. tdfn8 connections (top view) 1. sda and event are open drain. table 3. signal names pin symbol description direction 1 a0 serial bus address selection pin. can be tied to v ss or v dd . input 2 a1 serial bus address selection pin. can be tied to v ss or v dd . input 3 a2 serial bus address selection pin. can be tied to v ss or v dd . input 4v ss supply ground 5 sda (1) 1. sda and event are open drain. serial data input/output 6 scl serial clock input 7 event (1) event output pin. open drain and active-low. output 8v dd supply power (2.2 v to 3.6 v) ai12261 sda (1) v dd stts2004 v ss scl event (1) a 2 a 1 a 0 1 sda (1) gnd scl event (1) a1 a0 v dd a2 ai12262 2 3 4 8 7 6 5
serial communications stts2004 12/58 docid024229 rev 3 2.2 pin descriptions 2.2.1 a0, a1, a2 a2, a1, and a0 are selectable address pins for the 3 lsbs of the i 2 c interface address. these inputs must be tied to v dd or gnd as shown in figure 3 to provide 8 unique address selections. these pins are internally connected to the a2, a1, a0 (slave address inputs) of the eeprom. figure 3. device select code 2.2.2 v ss (ground) this is the reference for the power supply. it must be connected to system ground. 2.2.3 sda (open drain) this is the serial data input/output pin. sda(out) is an open drain output that may be wire- or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected from serial data (sda) to v dd . figure 20 indicates how the value of the pull-up resistor can be calculated. 2.2.4 scl this is the serial clock input pin. 2.2.5 event (open drain) this output pin is open drain and active-low. a pull-up resistor must be connected to this pin. 2.2.6 v dd (power) this is the supply voltage pin, and ranges from 2.2 v to 3.6 v. v dd v dd s tt s 2004 s tt s 2004 gnd gnd a(n) a(n)
docid024229 rev 3 13/58 stts2004 serial communications 58 figure 4. block diagram temperature sensor adc address pointer register 1 2 3 4 5 6 capability register configuration register temperature register upper register lower register critical register manufacturer id device id/ revision logic control comparator timing i 2 c interface 7 8 v dd scl sda a0 a1 a2 v ss event ai12278b page 1 4 kb spd eeprom block 3 block 2 page 0 block 1 block 0
temperature sensor operation stts2004 14/58 docid024229 rev 3 3 temperature sensor operation the temperature sensor continuously monitors the ambient temperature and updates the temperature data register. temperature data is latched internally by the device and may be read by software from the bus host at any time. the i 2 c slave address selection pins allow up to 8 such devices to co-exist on the same bus. this means that up to 8 memory modules can be supported, given that each module has one such slave device address slot. after initial power-on, the configuration registers are set to the default values. the software can write to the configuration register to set bits per the bit definitions in section 3.1: i 2 c communications . for details of operation and usage of 4 kb spd eeprom, refer to section 5: spd eeprom operation . 3.1 i 2 c communications the registers in this device are selected by the pointer register. at power-up, the pointer register is set to ?00?, which is the capability register location. the pointer register latches the last location it was set to. each data register falls into one of three types of user accessibility: 1. read-only 2. write-only, and 3. write/read same address a write to this device will always include the address byte and the pointer byte. a write to any register other than the pointer register, requires two data bytes. reading this device is achieved in one of two ways: ? if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will point to one of the read temperature registers because that will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieval of the two data bytes. ? if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. the data byte transfers the msb first. at the end of a read, this device can accept either an acknowledge (ack) or no acknowledge (no ack) status from the master. the no ack status is typically used as a signal for the slave that the master has read its last byte. this device subsequently takes up to 125 ms (max), 70 ms (typ) to measure the temperature for the default temperature resolution. note: the stts2004 does not initiate clock stretching which is an optional i 2 c bus feature.
docid024229 rev 3 15/58 stts2004 temperature sensor operation 58 figure 5. i 2 c write to pointer register figure 6. i 2 c write to pointer register, followed by a read data word ai12264 11 99 0 start by master address byte pointer byte ack by stts2004 ack by stts2004 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl sda ai12265 1919 ack by master no ack by master stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts2004 ack by stts2004 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl sda d9 d10 d11 d12 d13 d14 d15 d8 19 repeat start by master ack by stts2004 0 0 1 1 a2 a1 a0 r/w address byte scl (continued) sda (continued)
temperature sensor operation stts2004 16/58 docid024229 rev 3 figure 7. i 2 c write to pointer register, followed by a write data word 3.2 smbus/i 2 c ac timing consideration in order for this device to be both smbus- and i 2 c-compatible, it complies to a subset of each specification. the requirements which enable this device to co-exist with devices on either an smbus or an i 2 c bus include: ? the smbus minimum clock frequency is required ? the smbus timeout is maximum 35 ms ai14012 1919 ack by stts2004 no ack by stts2004 stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts2004 ack by stts2004 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl scl (continued) sda d8 d9 d10 d11 d12 d13 d14 d15 sda (continued)
docid024229 rev 3 17/58 stts2004 temperature sensor registers 58 4 temperature sensor registers the temperature sensor component is comprised of various user-programmable registers. these registers are required to write their corresponding addresses to the pointer register. they can be accessed by writing to their respective addresses (see table 4 ). pointer register bits 7 - 4 must always be written to '0' (see table 5 ). this must be maintained, as not setting these bits to '0' may keep the device from performing to specifications. the main registers include: ? capability register (read-only) ? configuration register (read/write) ? temperature register (read-only) ? temperature trip point registers (read/write) , including ? alarm temperature upper boundary ? alarm temperature lower boundary ? critical temperature ? manufacturer id register (read-only) ? device id and device revision id register (read-only) ? temperature resolution register (tres) (read/write) see table 6 on page 18 for pointer register selection bit details. note: registers beyond the specified (00-08) are reserved for stmicroelectronics? internal use only, for device test modes in product manufacturing. the registers must not be accessed by the user (customer) in the system application or the device may not perform according to specifications. table 4. temperature sensor registers summary address (hex) register name power-on default not applicable address pointer undefined 00 capability b-grade 0x00ef 01 configuration 0x0000 02 alarm temperature upper boundary trip 0x0000 03 alarm temperature lower boundary trip 0x0000 04 critical temperature trip 0x0000 05 temperature undefined 06 manufacturer?s id 0x104a 07 device id/revision 0x2201 08 temperature resolution register 0x0001
temperature sensor registers stts2004 18/58 docid024229 rev 3 4.1 capability register (read-only) this 16-bit register is read-only, and provides the ts capabilities which comply with the minimum jedec tse2004av specifications (see table 7 and table 8 on page 19 ). the stts2004 resolution is programmable via writing to pointer 08 register. the power-on default value is 0.25 c/lsb (10-bit). table 5. pointer register format msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 p3 p2 p1 p0 pointer/register select bits table 6. pointer register select bits (type, width, and default values) p3 p2 p1 p0 name register description width (bits) type (r/ w) default state (por) 0 0 0 0 capa thermal sensor capabilities b-grade only 16 r 00 ef 0 0 0 1 conf configuration 16 r/ w 00 00 0 0 1 0 upper alarm temperature upper boundary 16 r/ w 00 00 0 0 1 1 lower alarm temperature lower boundary 16 r /w 00 00 0 1 0 0 critical critical temperature 16 r/ w 00 00 0 1 0 1 temp temperature 16 r 00 00 0 1 1 0 manu manufacturer id 16 r 10 4a 0 1 1 1 id device id/revision 16 r 22 01 1 0 0 0 tres temperature resolution register 8 r/ w01 table 7. capability register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu rfu rfu rfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 evsd tmout v hv tres1 tres0 wider range higher precision alarm and critical trips
docid024229 rev 3 19/58 stts2004 temperature sensor registers 58 table 8. capability register bit definitions bit definition 0 basic capability ? 0 = alarm and critical trips turned off. ? 1 = alarm and critical trips turned on. 1 accuracy ? 1 = high accuracy 1 c over the active range and 2 c over the monitoring range (b-grade) (default) . 2 range width ? 0 = values lower than 0 c will be clamped and represented as binary value '0'. ? 1 = temperatures below 0 c can be read and the sign bit will be set accordingly. 4:3 temperature resolution ? 00 = 9 bit, 0.5 c/lsb ? 01 = 10 bit, 0.25 c/lsb - default resolution ? 10 = 11 bit, 0.125 c/lsb ? 11 = 12 bit, 0.0625 c/lsb 5 (v hv ) high voltage support for a0 (pin 1) ? 1 = stts2004 supports a voltage up to 10 volts on the a0 pin - (default) 6 tmout - bus timeout support ? 1 = default for stts2004-smbus compatible 25 ms - 35 ms 7 evsd - event behavior upon shutdown (default) ? 1 = the event pin output is deasserted (not driven) when entering shutdown, and remains deasserted upon exit from shutdown until the next thermal sample is taken, or possibly sooner if event is programmed for comparator mode. in interrupt mode, event may or may not be asserted when exiting shutdown if a pending interrupt has not been cleared. 15:8 reserved these values must be set to '0'.
temperature sensor registers stts2004 20/58 docid024229 rev 3 4.2 configuration register (read/write) the 16-bit configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and jedec requirements (see table 9 on page 21 and table 10 on page 21 ). 4.2.1 event thresholds all event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through 9) to be set when they de-assert. 4.2.2 interrupt mode the interrupt mode allows an event to occur where software may write a '1' to the clear event bit (bit 5) to de-assert the event interrupt output until the next trigger condition occurs. 4.2.3 comparator mode the comparator mode enables the device to be used as a thermostat. reads and writes on the device registers will not affect the event output in comparator mode. the event signal will remain asserted until temperature drops outside the range or is re-programmed to make the current temperature ?out of range?. 4.2.4 shutdown mode the stts2004 features a shutdown mode which disables all power-consuming activities (e.g. temperature sampling operations), and leaves the serial interface active. this is selected by setting the shutdown bit (bit 8) to '1'. in this mode, the devices consume the minimum current (i shdn ), as shown in table 30 on page 44 . note: bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'. the device may be enabled for continuous operation by clearing bit 8 to '0'. in shutdown mode, all registers may be read or written to. power recycling will also clear this bit and return the device to continuous mode as well. if the device is shut down while the event pin is asserted, then the event output will be de- asserted during shutdown. it will remain de-asserted until the device is enabled for normal operation. once the device is enabled, it takes t conv before the device can re-assert the event output.
docid024229 rev 3 21/58 stts2004 temperature sensor registers 58 the temperature sensor configuration register holds the control and status bits of the event pin as well as general hysteresis on all limits. to avoid glitches on the event output pin, users should disable event or critical functions prior to programming or changing other device configuration settings. table 9. configuration register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu hysteresis hysteresis shutdown mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode table 10. configuration register bit definitions bit definition 0 event mode ? 0 = comparator output mode (this is the default). ? 1 = interrupt mode; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it is unlocked. 1 event polarity (1) the event polarity bit controls the active state of the event pin. the event pin is driven to this state when it is asserted. ? 0 = active-low (this is the default). requires a pull-up resistor to set the inactive state of the open-drain output. the power to the pull-up resistor should not be greater than v dd + 0.2 v. active state is logical ?0?. ? 1 = active-high. the active state of the pin is then logical ?1?. 2 critical event only ? 0 = event output on alarm or critical temperature event (this is the default). ? 1 = event only if the temperature is above the value in the critical temperature register (t a > t crit ); when the alarm window lock bit (bit6) is set, this bit cannot be altered until it is unlocked. 3 event output control ? 0 = event output disabled (this is the default). ? 1 = event output enabled; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it is unlocked. 4 event status (read-only) (2) ? 0 = event output condition is not being asserted by this device. ? 1 = event output condition is being asserted by this device via the alarm window or critical trip event. 5 clear event (write-only) (3) ? 0 = no effect. ? 1 = clears the active event in interrupt mode. the pin is released and will not assert until a new interrupt condition occurs.
temperature sensor registers stts2004 22/58 docid024229 rev 3 6 alarm window lock bit ? 0 = alarm trips are not locked and can be altered (this is the default). ? 1 = alarm trip register settings cannot be altered. this bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 7 critical trip lock bit ? 0 = critical trip is not locked and can be altered (this is the default). ? 1 = critical trip register settings cannot be altered. this bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 8 shutdown mode ? 0 = ts is enabled, continuous conversion (this is the default). ? 1 = shutdown ts when the shutdown, device, and a/d converter are disabled in order to save power. no event conditions will be asserted; when either of the lock bits (bit6 or bit7) is set, then this bit cannot be altered until it is unlocked. it can be cleared at any time. 10:9 hysteresis enable (see figure 8 and table 11 ) ? 00 = hysteresis is disabled (default) ? 01 = hysteresis is enabled at 1.5 c ? 10 = hysteresis is enabled at 3 c ? 11 = hysteresis is enabled at 6 c hysteresis applies to all limits when the temperature is dropping below the threshold so that once the temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to be flagged as an interrupt event. note that hysteresis is also applied to the event pin functionality. when either of the lock bits is set, these bits cannot be altered. 15:11 reserved for future use. these bits will always read ?0? and writing to them will have no effect. for future compatibility, all rfu bits must be programmed as ?0?. 1. as this device is used in dimm (memory modules) applications, it is strongly recommended that only the active-low polarity (default) is used. this will provide full compatibility with the stts2002. this is the recommended configuration for the stts2004. 2. the actual incident causing the event can be determined from the read temperature register. interrupt events can be cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning). 3. writing to this register has no effect on overall device functioning in comparator mode. when read, this bit will always return a logic '0' result. table 10. configuration register bit definitions (continued) bit definition
docid024229 rev 3 23/58 stts2004 temperature sensor registers 58 figure 8. hysteresis 1. t h = value stored in the alarm temperature upper boundary trip register 2. t l = value stored in the alarm temperature lower boundary trip register 3. hys = absolute value of selected hysteresis below window bit above window bit t h - hys t l - hys t h t l ai12270 table 11. hysteresis as applied to temperature movement below alarm window bit above alarm window bit temperature slope temperature threshold temperature slope temperature threshold sets falling t l - hys rising t h clears rising t l falling t h - hys
temperature sensor registers stts2004 24/58 docid024229 rev 3 4.2.5 event output pin functionality the stts2004 event pin is an open drain output that requires a pull-up to v dd on the system motherboard or integrated into the master controller. event has three operating modes, depending on configuration settings and any current out-of-limit conditions. these modes are interrupt, comparator or critical. in interrupt mode the event pin will remain asserted until it is released by writing a ?1? to the ?clear event? bit in the status register. the value to write is independent of the event polarity bit. in comparator mode the event pin will clear itself when the error condition that caused the pin to be asserted is removed. in the critical mode the event pin will only be asserted if the measured temperature exceeds the critical limit. once the pin has been asserted, it will remain asserted until the temperature drops below the critical limit minus hysteresis. figure 9 on page 25 illustrates the operation of the different modes over time and temperature. when the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense temperature movement around trigger points. for example, when using the ?above alarm window? bit (temperature register bit 14, see table 13 on page 26 ) and hysteresis is set to 3 c, as the temperature rises, bit 14 is set (bit 14 = 1). the temperature is above the alarm window and the temperature register contains a value that is greater than the value set in the alarm temperature upper boundary register (see table 17 on page 28 ). if the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the alarm temperature upper boundary register minus 3 c (see figure 8 on page 23 and table 11 on page 23 for details. similarly, when using the ?below alarm window? bit (temperature register bit 13, see table 13 on page 26 ) will be set to '0'. the temperature is equal to or greater than the value set in the alarm temperature lower boundary register (see table 18 on page 28 ). as the temperature decreases, bit 13 will be set to '1' when the value in the temperature register is less than the value in the alarm temperature lower boundary register minus 3 c (see figure 8 on page 23 and table 11 on page 23 for details. if the device enters the shutdown mode with the event output asserted, the output will be de-asserted. once the shutdown bit is cleared, the event output will do the following, based on whether the device is configured for comparator or interrupt modes: comparator mode the event output will remain de-asserted until after the first temperature conversion (t conv ) is completed. after this initial temperature conversion, t a must satisfy the t upper or t lower boundary conditions in order for the event output to be asserted. interrupt mode the event output will remain de-asserted until after the first temperature conversion (t conv ) is completed. if the clear event bit (bit 5 of configuration register) is never set, then the event output will re-assert after the first temperature conversion.
docid024229 rev 3 25/58 stts2004 temperature sensor registers 58 figure 9. event output boundary timings systems that use the active high mode for event output must be wired point-to-point between the stts2004 and the sensing controller. wire-or configurations should not be used with active high event output since any device pulling the event output signal low will mask the other devices on the bus. also note that the normal state of event output in active high mode is a ?0? which will constantly draw power through the pull-up resistor. table 12. legend for figure 9: event output boundary timings note event output boundary conditions event output t a bits comparator interrupt critical 15 14 13 1t a ? t lower hlh000 2t a ?? t lower - t hys llh001 3t a ? ? ? t upper llh010 4t a ?? t upper - t hys hlh000 5t a ? t crit lll100 6t a ?? t crit - t hys lhh010 7 when t a ? t crit and t a < t crit - t hys , the event output is in comparator mode and bit 0 of the configuration register (interrupt mode) is ignored. comparator t crit t upper t lower t a t lower - t hys interrupt s/w int. clear critical event output (active low) t upper - t hys t crit - t hys t upper - t hys t lower - t hys 1213357 4642 ai12271 note:
temperature sensor registers stts2004 26/58 docid024229 rev 3 4.3 temperature register (read-only) this 16-bit, read-only register stores the temperature measured by the internal band gap ts as shown in table 13 . when reading this register, the msbs (bit 15 to bit 8) are read first, and then the lsbs (bit 7 to bit 0) are read. the result is the current-sensed temperature. the data format is 2s complement with one lsb = 0.25 c for the default resolution. the msb has a 128 c resolution. the trip status bits represent the internal temperature trip detection, and are not affected by the status of the event or configuration bits (e.g. event output control or clear event). if neither of the above or below values are set (i.e. both are 0), then the temperature is exactly within the user-defined alarm window boundaries. 4.3.1 temperature format the 16-bit value used in the trip point set and temperature read-back registers is 2s complement, with the lsb equal to 0.0625 c (see table 13 ). for example: 1. a value of 019c h represents 25.75 c 2. a value of 07c0 h represents 124 c, and 3. a value of 1e74 h represents ?24.75 c all unused resolution bits are set to zero. the msb will have a resolution of 128 c. the stts2004 supports programmable resolutions (9-12 bits) which is 0.5 to 0.0625 c/lsb. the default is 0.25 c/lsb (10 bits) programmable. the upper 3 bits indicate trip status based on the current temperature, and are not affected by the event output status. table 13. temperature register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (2) bit 0 (3) flag bit flag bit flag bit sign 128 64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625 c/lsb above critical input (4) above alarm window (4) below alarm window (4) temperature (default - 10 bit) 0 0 flag bits example hex value of 07c0 corresponds to 124 c (10-bit) 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 07c0 h flag bits example hex value of 1ec0 corresponds to ?20 c (10-bit) 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 1ec0 h 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value. 4. see table 15 for explanation.
docid024229 rev 3 27/58 stts2004 temperature sensor registers 58 a 0.25 c minimum granularity is supported in all registers. examples of valid settings and interpretation of temperature register bits for 10-bit (0.25 c) default resolution are provided in table 14 . 4.4 temperature trip point registers (read/write) the stts2004 alarm mode registers provide for 11-bit data in 2s compliment format. the data provides for one lsb = 0.25 c. all unused bits in these registers are read as '0'. the stts2004 has three temperature trip point registers (see table 16 ): ? alarm temperature upper boundary threshold ( table 17 ) ? alarm temperature lower boundary threshold ( table 18 ), and ? critical temperature trip point value ( table 19 ) note: if the upper or lower boundary threshold values are being altered in-system, all interrupts should be turned off until a known state can be obtained to avoid superfluous interrupt activity. table 14. temperature register coding examples (for 10 bits) b15:b0 (binary) value units xxx0 0000 0010 11xx +2.75 c xxx0 0000 0001 00xx +1.00 c xxx0 0000 0000 01xx +0.25 c xxx0 0000 0000 00xx 0 c xxx1 1111 1111 11xx ?0.25 c xxx1 1111 1110 00xx ?1.00 c xxx1 1111 1101 11xx ?2.25 c xxx1 1110 1100 00xx ?20.00 c table 15. temperature register bit definitions bit definition with hysteresis = 0 13 below (temperature) alarm window ? 0 = temperature is equal to or above the alarm window lower boundary temperature. ? 1 = temperature is below the alarm window. 14 above (temperature) alarm window. ? 0 = temperature is equal to or below the alarm window upper boundary temperature. ? 1 = temperature is above the alarm window. 15 above critical trip ? 0 = temperature is below the critical temperature setting. ? 1 = temperature is equal to or above the critical temperature setting.
temperature sensor registers stts2004 28/58 docid024229 rev 3 4.4.1 alarm window trip the device provides a comparison window with an upper temperature trip point in the alarm upper boundary register, and a lower trip point in the alarm lower boundary register. when enabled, the event output will be triggered whenever entering or exiting (crossing above or below) the alarm window. 4.4.2 critical trip the device can be programmed in such a way that the event output is only triggered when the temperature exceeds the critical trip point. the critical temperature setting is programmed in the critical temperature register. when the temperature sensor reaches the critical temperature value in this register, the device is automatically placed in comparator mode, which means that the critical event output cannot be cleared by using software to set the clear event bit. table 16. temperature trip point register format p3 p2 p1 p0 name register description width (bits) type (r/ w) default state (por) 0 0 1 0 upper alarm temperature upper boundary 16 r/ w 00 00 0 0 1 1 lower alarm temperature lower boundary 16 r/ w 00 00 0 1 0 0 critical critical temperature 16 r/ w 00 00 table 17. alarm temperature upper boundary register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (2) 1 bit (3) 0 000 alarm window upper boundary temperature 00 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value. table 18. alarm temperature lower boundary register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (2) 1 bit (3) 0 000 alarm window lower boundary temperature 00 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value.
docid024229 rev 3 29/58 stts2004 temperature sensor registers 58 note: in all temperature register formats bits 0 and bits 1 are used when the resolution is more than 10 bits. these registers show temperature data for the default 10 bits. 4.5 manufacturer id register (read-only) the manufacturer?s id (programmed value 104ah) in this register is the stmicroelectronics identification provided by the peripheral component interconnect special interest group (pcisig). table 19. critical temperature register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit (2) 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (3) 1 bit (4) 0 000 critical temperature trip point 00 1. bit 2 is lsb for default 10-bit mode. 2. if critical trip lockout bit (bit 7 of configuration register in table 10 ) is set, then this register becomes read-only. 3. depending on status of the resolution register, bit 1 may display 0.125 c value. 4. depending on status of the resolution register, bit 0 may display 0.0625 c value. table 20. manufacturer id register (read-only) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00010000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01001010
temperature sensor registers stts2004 30/58 docid024229 rev 3 4.6 device id and device revision id register (read-only) the device ids and device revision ids are maintained in this register. the register format is shown in table 21 . the device ids and device revision ids reflect the current device. the current device id and revision id value is 2201 h. 4.7 temperature resolution register (read/write) with this register a user can program the temperature sensor resolution from 9-12 bits as shown below. the power-on default is always 10 bit (0.25 c/lsb). the selected resolution is also reflected in bits (4:3) (tres1:tres0) of the capability register. the default value is 01 for tres register. table 21. device id and device revision id register (read-only) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00100010 device id bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000001 device revision id table 22. temperature resolution register (tres) (read/write) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000001 resolution section register resolution bits table 23. tres details resolution register bits bit1 bit0 c/lsb bits conversion time (max) 0 0 0.5 9 65 ms 0 1 0.25 10 125 ms (default) 1 0 0.125 11 250 ms 1 1 0.0625 12 500 ms
docid024229 rev 3 31/58 stts2004 temperature sensor registers 58 4.8 smbus timeout the stts2004 supports the smbus timeout feature. if the host holds scl low for more than t timeout (max), the stts2004 resets itself and releases the bus. this feature is supported even when the device is in shutdown mode and when the device is driving sda low. figure 10. smbus timeout timing diagram scl sc l t timeout (min) t timeout (max) scl low < t timeout (min), device will not device detects scl low t timeout (min ) sc l device may or may not reset bus communication and resets bus communication by t timeout (max) reset bus communication
temperature sensor registers stts2004 32/58 docid024229 rev 3 4.9 device reset and initialization in order to prevent inadvertent operations during power-up, a power-on reset (por) circuit is included. upon a cold power-on, v dd must rise monotonically between v pon and v dd (min) without ringback to ensure proper startup. once v dd has passed the v pon threshold, the device is reset. prior to selecting the memory and issuing instructions, a valid and stable v dd voltage must be applied, and no command may be issued to the device for t init . the supply voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). at power-down (phase during which v dd decreases continuously), as soon as v dd drops from the normal operating voltage below the minimum operating voltage, the device stops responding to commands. upon warm power cycling, v dd must remain below v poff for the period t poff , and must meet cold power-on reset timing when restoring power. note: if v dd drops below v pon but stays above v poff, for less than or greater than t poff , and then returns to v dd (min), a por may occur. figure 11. stts2004 reset and initialization power-up conditions the v dd voltage has to rise continuously from 0 v up to the minimum v dd operating voltage defined in table 29 and the rise time must not vary faster than 1 v/ s. v poff v poff v pon v dd (min) cold power warm power on reset on reset v dd ramp up and ramp down t poff first command t init
docid024229 rev 3 33/58 stts2004 spd eeprom operation 58 5 spd eeprom operation 5.1 4 kb spd eeprom operation the stts2004 includes a 4-kbit serial eeprom organized as two pages of 256 bytes each, or 512 bytes of total memory. each page is composed of two 128-byte blocks. the devices are able to selectively lock the data in any or all of the four 128-byte blocks. the spd is a 512-byte eeprom device designed to operate the two-wire bus at a maximum of 1 mhz transfer rate, in the 2.2 v - 3.6 v voltage range. the spd in the stts2004 is protocol-compatible with the previous operation in the stts2002. the page selection method allows commands used with the stts2002 to be applied to the lower or upper pages of the eeprom. individually locking a 128-byte block may be accomplished using a software write protection mechanism in conjunction with a high input voltage v hv on input a0. by sending the device a specific smbus sequence, each block may be protected from writes until the write protection is electrically reversed using a separate i 2 c sequence which also requires v hv on input a0. the write protection for all four blocks is cleared simultaneously, and may be re-asserted after being cleared. 5.2 internal device reset - spd eeprom in order to prevent inadvertent write operations during power-up, a power-on reset (por) circuit is included. at power-up (phase during which v dd is lower than v dd min but increases continuously), the device will not respond to any instruction until v dd has reached the power-on reset threshold voltage (this threshold is lower than the minimum v dd operating voltage defined in table 29: operating and ac measurement conditions ). once v dd has passed the por threshold, the device is reset. prior to selecting the memory and issuing instructions, a valid and stable v dd voltage must be applied. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). at power-down (phase during which v dd decreases continuously), as soon as v dd drops from the normal operating voltage below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 5.3 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit slave address (a2, a1, a0). to address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. up to eight stts2004 spd devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the slave address (a0, a1, a2) inputs. when the device select
spd eeprom operation stts2004 34/58 docid024229 rev 3 code is received, the device only responds if the slave address is the same as the value on the slave address (a0, a1, a2) inputs. the 8 th bit is the read/ w rite bit (r w). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. the operating modes are detailed in table 24 . 5.4 setting the write protection there are four independent memory blocks, and each block may be independently protected. the memory blocks are: ? block 0 = memory addresses 0x00 to 0x7f (decimal 0 to 127), page address = 0 ? block 1 = memory addresses 0x80 to 0xff (decimal 128 to 255), page address = 0 ? block 2 = memory addresses 0x00 to 0x7f (decimal 0 to 127), page address = 1 ? block 3 = memory addresses 0x80 to 0xff (decimal 128 to 255), page address = 1 the device has three software commands for setting, clearing, or interrogating the write protection status. ? swpn: set write protection for block n ? cwp: clear write protection for all blocks ? rpsn: read protection status for block n the level of write protection (set or cleared), that has been defined using these instructions, remains defined even after a power cycle. the dtics of the swp, cwp, and rps instructions are defined in table 2 . 5.4.1 set and clear the write protection (swpn and cwp) if the software write protection has been set with the swpn instruction, it may be cleared again with a cwp instruction. swpn acts on a single block as specified in the swpn command, but cwp clears the write protection for all blocks. when decoded, swpn and cwpn trigger a write cycle lasting t w (see table 33 ). the dtics of the swp and cwp instructions are defined in table 2 . table 24. operating modes mode r w bit bytes initial sequence current address read 1 1 start, device select, r w = 1 random address read 0 1 start, device select, r w = 0, address 1 restart, device select, r w = 1 sequential read 1 ? 1 similar to current or random address read byte write 0 1 start, device select, r w = 0 page write 0 ?? 16 start, device select, r w = 0 ts write 0 2 start, device select, r/ w = 0, pointer data, stop ts read 1 2 start, device select, r/ w = 1, pointer data, stop
docid024229 rev 3 35/58 stts2004 spd eeprom operation 58 figure 12. setting the write protection 5.4.2 rpsn: read protection status the controller issues an rpsn command specifying which block to report upon. if the software write protection has not been set, the device replies to the data byte with an ack. if it has been set, the device replies to the data byte with a noack. 5.4.3 span: set spd page address the controller issues an span command to select the lower 256 bytes (spa0) or upper 256 bytes (spa1). after a cold or warm power-on reset, the spd page address is always 0, selecting the lower 256 bytes. 5.4.4 rpa: read spd page address the controller issues an rpa command to determine if the currently selected spd page is 0 (device returns ack) or 1 (device returns noack). 5.5 write operations following a start condition, the bus master sends a device select code with the r w bit reset to 0. the device acknowledges this, as shown in figure 13 , and waits for an address byte. the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. start sda line ai01935b ack word address value (don't care) ack data value (don't care) stop ack control byte bus activity master bus activity
spd eeprom operation stts2004 36/58 docid024229 rev 3 5.5.1 byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the location is not modified. if, instead, the addressed location is not write- protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 13 . figure 13. write mode sequences in a non write-protected area 5.5.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control ( wc) is low. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the locations are not modified. after each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. 5.5.3 minimizing system delays by polling on ack the sequence, as shown in figure 14 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). ? step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). s top s t a rt byte write device s elect byte a ddre ss d a t a in s t a rt p a ge write device s elect byte a ddre ss d a t a in 1 d a t a in 2 ai01941 b s top d a t a in n ack ack ack r/w ack ack ack r/w ack ack
docid024229 rev 3 37/58 stts2004 spd eeprom operation 58 figure 14. write cycle polling flowchart using ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 33 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. 5.6 read operations read operations are performed independently of whether a hardware or software protection has been set. the device has an internal address counter which is incremented each time a byte is read. 5.6.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 15 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. write cycle in progre ss ai01 8 47d next oper a tion i s a ddre ss ing the memory s t a rt condition device s elect with rw = 0 ack ret u rned ye s no ye s no re s t a rt s top d a t a for the write oper a tion device s elect with rw = 1 s end a ddre ss a nd receive ack fir s t b yte of in s tr u ction with rw = 0 a lre a dy decoded b y the device ye s no s t a rt condition contin u e the write oper a tion contin u e the r a ndom read oper a tion
spd eeprom operation stts2004 38/58 docid024229 rev 3 5.6.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the rw bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 15 , without acknowledging the byte. 5.6.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 15 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.6.4 acknowledge in read mode for all read commands, after each byte read, the device waits for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during thistime, the device terminates the data transfer and switches to its standby mode.
docid024229 rev 3 39/58 stts2004 spd eeprom operation 58 figure 15. read mode sequences start dev sel (1) byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel (1) data out sequential current read stop data out n start dev sel (1) byte addr sequential random read start dev sel (1) data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
use in a memory module stts2004 40/58 docid024229 rev 3 6 use in a memory module in the dual in line memory module (dimm) application, the spd is soldered directly on to the printed circuit module. the three slave address inputs (a0, a1, a2) must be connected to v ss or v dd directly (that is without using a pull-up or pull-down resistor) through the dimm socket (see table 25 ). 6.1 programming the spd the spd eeprom can be programmed when: ? the dimm is isolated (not inserted on the pcb motherboard) ? the dimm is inserted on the pcb motherboard 6.1.1 isolated dimm with specific programming equipment, it is possible to define the spd eeprom content using byte and page write instructions, and to set its write-protection using the swpn and cwp instructions. to issue the swpn and cwp instructions, the dimm must be inserted in the application-specific slot where the a0 signal must be driven to v hv during the whole instruction. this programming step is mainly intended for use by dimm makers, whose end- application manufacturers will want to clear this write-protection with the cwp on their own specific programming equipment, to modify the protection bytes. the read protection status (rpsn), set spd page address (span), and the read spd page address (rpa) commands are fully supported when the dimm is isolated. table 25. dram dimm connections dimm position a2 a1 a0 0 v ss (0) v ss (0) v ss (0) 1 v ss (0) v ss (0) v dd (1) 2 v ss (0) v dd (1) v ss (0) 3 v ss (0) v dd (1) v dd (1) 4 v dd (1) v ss (0) v ss (0) 5 v dd (1) v ss (0) v dd (1) 6 v dd (1) v dd (1) v ss (0) 7 v dd (1) v dd (1) v dd (1)
docid024229 rev 3 41/58 stts2004 use in a memory module 58 6.1.2 dimm inserted in the application motherboard as the final application cannot drive the a0 pin to v hv , this option is not available. table 26 and table 27 show how the ack bits can be used to identify the write-protection status. table 26. acknowledge when writing data or defining the write-protection status (instructions with r/w_n bit = 0) status instruction ack address ack data byte ack write cycle (t w ) protected swpn noack not significant noack not significant noack no cwp ack not significant ack not significant ack yes page or byte write in protected block ack address ack data noack no not protected swpn or cwp ack not significant ack not significant ack yes page or byte write ack address ack data ack yes table 27. acknowledge when reading the protection status (instructions with r/w_n bit = 1) swpn status instruction ack address ack data byte ack set rpsn noack not significant noack not significant noack not set rpsn ack not significant noack not significant noack
use in a memory module stts2004 42/58 docid024229 rev 3 figure 16. serial presence detect block diagram 1. a2, a1 and a0 are wired at each dram module slot in a binary sequence for a maximum of 8 devices. 2. common clock and common data are shared across all the devices. r pu a2 v dd a1 a0 a2 a1 a0 a2 a1 a0 a2 a1 a0 a2 a1 a0 a2 a1 a0 a2 a1 a0 a2 a1 a0 v dd v dd v dd v ss v ss v dd v dd v ss v dd v ss v dd v ss v ss v ss v ss r pu
docid024229 rev 3 43/58 stts2004 maximum ratings 58 7 maximum ratings stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 28. absolute maximum ratings symbol parameter value unit t stg storage temperature ?65 to 150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage a0 v ss ? 0.3 to 10.0 v others v ss ? 0.3 to 4.3 v v dd supply voltage v ss ? 0.3 to 4.3 v i o output current 10 ma p d power dissipation 320 mw ? ja thermal resistance 87.4 c/w
dc and ac parameters stts2004 44/58 docid024229 rev 3 8 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 29 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 17. ac measurement i/o waveform table 29. operating and ac measurement conditions parameter conditions unit v dd supply voltage 2.2 to 3.6 v operating temperature ?20 to 125 c input rise and fall times ? 50 ns load capacitance 100 pf input pulse voltages 0.2v dd to 0.8v dd v input and output timing reference voltages 0.3v dd to 0.7v dd v input levels input and output timing reference levels 0.8 * v dd 0.2 * v dd 0.7 * v dd 0.3 * v dd ai14011 table 30. dc characteristics - temperature sensor component with eeprom sym description test condition (1) min typ (2) max unit v dd supply voltage 2.2 3.3 3.6 v i dd v dd supply current (no load) eeprom active (3) f = 1000 khz 0.4 2.0 ma eeprom standby, f = 1000 khz 160 350 a i ddw v dd supply current (write) v dd = 3.3 v, f = 1000 khz (4) 3ma i dd1 shutdown mode supply current eeprom standby, ts shutdown 35 a i ili input leakage current (scl, sda) v in = v ss or v dd 5 a i ilo output leakage current v out = v ss or v dd , sda in hi-z 5 a
docid024229 rev 3 45/58 stts2004 dc and ac parameters 58 v il input logic low scl, sda, a0-a2 ?0.5 0.3v dd v v ih input logic high scl, sda, a0-a2 0.7v dd v dd + 1.0 v f scl i 2 c clock frequency 10 1000 khz t timeout smbus timeout 25 35 ms v hv a0 high voltage v hv ?? v dd ?? 4.8 v 7 10 v v ol1 output low voltage i ol = 3.0 ma, v dd > 2.2 v 0.4 v i ol low-level output current v ol = 0.4 v 20 ma v hyst input hysteresis (scl, sda) 0.05v dd v v pon power-on reset (por) threshold monotonic rise between v pon and v dd (min) without ringback 1.6 v v poff power-off threshold for warm power-on cycle 0.9 v v pu event pin pull-up voltage v dd + 1.0 v 1. guaranteed operating temperature for combined module: t a = ?20 c to 125 c; v dd = 2.2 v to 3.6 v (except where noted). 2. typical numbers taken at v dd = 3.3 v, t a = 25 c. 3. read current only 4. verified by design and characterization, not necessarily tested on all devices table 30. dc characteristics - temperature sensor component with eeprom (continued) sym description test condition (1) min typ (2) max unit
dc and ac parameters stts2004 46/58 docid024229 rev 3 figure 18. smbus/i 2 c timing diagram table 31. input parameters symbol parameter (1) test condition min max units c in input capacitance 8 pf z ail a0, a1, a2 input impedance v in < 0.3 v dd 30 k ? z aih a0, a1, a2 input impedance v in > 0.7 vdd 800 k ? t sp spike suppression pulse width of spikes that must be suppressed by the input filter on scl and sda 50 ns 1. verified by design and characterization, not necessarily tested on all devices table 32. temperature to digital conversion performance symbol parameter test condition min typ max units b-grade accuracy for corresponding range 2.2 v . vdd . 3.6 v +75 c < t a < +95 0.5 1.0 c +40 c < t a < +125 1.0 2.0 ?20 c < t a < +125 2.0 3.0 resolution 0.5 0.25 0.0625 c/lsb 9 10 12 bits t conv conversion time 10-bit - default 70 125 ms v ih v ih v ih v ih v il v il v il v il s cl s cl s da s da note: p s t a nd s for s top a nd s s t a nd s for s ta rt s top condition write cycle s ta rt condition t s u: s ta t s u: s to t w t buf t low t hd: s ta t hd:di t r t f t s u:dat t high t s u: s ta t hd:dat t s u: s to p s p s a i12266 a
docid024229 rev 3 47/58 stts2004 dc and ac parameters 58 table 33. ac characteristics of stts2004 for smbus and i 2 c compatibility timings symbol parameter min max units f scl i 2 c clock frequency 10 1000 khz t high clock high period 260 ? ns t low (1) 1. the stts2004 will not initiate clock stretching which is an i 2 c bus optional feature. clock low period 500 ? ns t r (2) 2. guaranteed by design and characterization, not necessarily tested. clock/data rise time ? 120 ns t f (2) clock/data fall time ? 120 ns t su:dat data-in setup time 50 ? ns t hd:di data-in hold time 0 ? ns t hd:dat data-out hold time 0 350 ns t su:sta (3) 3. for a restart condition, or following a write cycle. repeated start condition setup time 260 ? ns t hd:sta hold time after (repeated) start condition. after this period, the first clock cycle is generated. 260 ? ns t su:sto stop condition setup time 260 ? ns t buf bus free time between stop (p) and start (s) conditions 500 ? ns t w (4) 4. this parameter reflects maximum write time for eeprom. write time for eeprom ? 5 ms t timeout (5) 5. the i 2 c bus masters can terminate a transaction in process and reset devices on the bus by asserting scl low for t timeout,max or longer. the stts2004, upon detecting this condition, will reset communication and be able to receive a new start condition no later than t timeout,max . the stts2004 will not reset if scl stretching is less than t timeout,min . bus timeout 25 35 ms t poff warm power cycle off time 1 ? ms t init time from power-on to first command 10 ? ms c b (6) 6. the maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application. capacitive load for each bus line 550 pf
dc and ac parameters stts2004 48/58 docid024229 rev 3 figure 19. maximum r pu value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1 mhz figure 20. pull-up resistor values versus bus line capacitance 1 10 0 0 0 1 0 1 bus line capacitor (pf) bus line pull-up resistor (k ) master stts2004 r pu v cc c bus scl sda here, r pu c bus = 120 ns r p u c bu s = 150 ns 4 30 the r c bus time constant must be below the 150 ns time constant line represented on the left. 10 pu 200 220 230 250 270 300 330 375 430 500 600 750 1,000 1,500 2,000 2,800 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 maximum rpu ohms bus capacitance (pf) pull-up resistor values vs. bus capacitance - rc = 150 ns for f>400 khz rpu (ohm) c (pf) rpu (ohm) 750 200 700 220 650 230 600 250 550 270 500 300 450 330 400 375 350 430 300 500 250 600 200 750 150 1000 100 1500 75 2000 50 2800
docid024229 rev 3 49/58 stts2004 package mechanical data 58 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data stts2004 50/58 docid024229 rev 3 figure 21. t dfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) note: jedec mo-229, variation w2030d note: jedec mo-229, variation w2030d 8089094_a table 34. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) sym mm inches min typ max min typ max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.00 0.05 0.000 0.000 0.002 a3 0.20 0.008 b 0.20 0.25 0.30 0.008 0.010 0.012 d 1.95 2.00 2.05 0.077 0.079 0.081 d2 1.35 1.40 1.45 0.053 0.055 0.057 e 2.95 3.00 3.05 0.116 0.118 0.120 e2 1.25 1.30 1.35 0.049 0.051 0.053 e 0.50 0.020 l 0.30 0.35 0.40 0.012 0.014 0.016 ddd 0.08 0.003
docid024229 rev 3 51/58 stts2004 package mechanical data 58 figure 22. dn package topside marking information (tdfn8) 1. temperature grade and package b = b-grade, stacked 2 = minimum operating voltage of 2.2 v dn = 0.80 mm tdfn package 2. device name tse4 = stts2004 3. traceability codes ai13907c tse4 (2) xxxx (3) b2dn (1)
package mechanical data stts2004 52/58 docid024229 rev 3 the landing pattern recommendations per the jedec proposal for the tdfn package (dn) are shown in figure 23 . the preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for modules with tight routing requirements. figure 23. landing pattern - tdfn8 package (dn) e/2 e/2 e2 k k e2/2 e2/2 e2 d2/2 d2 d2/2 l l e b b b2 b4 k2 k2 k2 e3 e3 e4 ai14000
docid024229 rev 3 53/58 stts2004 package mechanical data 58 table 35 lists variations of landing pattern implementations, ranked as ?preferred? and minimum acceptable? based on the jedec proposal. table 35. parameters for landing pattern - tdfn8 package (dn) parameter description dimension min nom max d2 heat paddle width 1.40 - 1.60 e2 heat paddle height 1.40 - 1.60 e3 heat paddle centerline to contact inner locus 1.00 - - l contact length 0.70 - 0.80 k heat paddle to contact keepout 0.20 - - k2 contact to contact keepout 0.20 - - e contact centerline to contact centerline pitch for inner contacts - 0.50 - b contact width for inner contacts 0.25 - 0.30 e2 landing pattern centerline to outer contact centerline, ?minimum acceptable? option (1) - 0.50 - b2 corner contact width, ?minimum acceptable option? (1) 0.25 - 0.30 e4 landing pattern centerline to outer contact centerline, ?preferred? option (2) - 0.60 - b4 corner contact width, ?preferred? option (2) 0.45 - 0.50 1. minimum acceptable option to be used when routing prevents preferred width contact. 2. preferred option to be used when possible.
package mechanical data stts2004 54/58 docid024229 rev 3 figure 24. carrier tape for tdfn8 package t k 0 p 1 a 0 b 0 p 2 p 0 center lines of cavity w e f d top cover tape user direction of feed am0 3 07 3 v1 table 36. carrier tape dimensions tdfn8 package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 t unit bulk qty tdfn8 8.00 ? 0.30 ?0.10 1.50 +0.10/ ?0.00 1.75 ? 0.10 4.00 ? 0.10 2.00 ? 0.10 3.50 ? 0.05 2.30 ? 0.10 3.20 ? 0.10 1.10 ? 0.10 4.00 ? 0.10 0.30 ? 0.05 mm 3000
docid024229 rev 3 55/58 stts2004 package mechanical data 58 figure 25. reel schematic note: the dimensions given in table 37 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 37. reel dimensions for 8 mm carrier tape - tdfn8 package a (max) b (min) c d (min) n (min) g t (max) 180 mm (7-inch) 1.5 mm 13 mm ?? 0.2 mm 20.2 mm 60 mm 8.4 mm + 2/?0 mm 14.4 mm
part numbering stts2004 56/58 docid024229 rev 3 10 part numbering table 38. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stts2004 b 2 dn 3 f device stts2004 accuracy grade b: maximum accuracy 75 c to 95 c = ?? 1 c voltage 2 = 2.2 v - 3.6 v package dn = tdfn8 temperature range 3 = ?20 c to 125 c shipping method f = ecopack ? package, tape & reel packing
docid024229 rev 3 57/58 stts2004 revision history 58 11 revision history table 39. document revision history date revision changes 22-feb-2013 1 initial release 28-aug-2013 2 document status promoted from preliminary to production data updated table 30: dc characteristics - temperature sensor component with eeprom added table 31: input parameters added table 32: temperature to digital conversion performance moved figure 18: smbus/i 2 c timing diagram to section 8 updated and moved table 33: ac characteristics of stts2004 for smbus and i 2 c compatibility timings to section 8 18-oct-2013 3 updated v pu in table 30: dc characteristics - temperature sensor component with eeprom
stts2004 58/58 docid024229 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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